1. Field of the Invention
The present invention generally relates to probe cards with vertical needles, and more specifically, to an improved probe card with a vertical needle which enables wafer testing in shorter time and which can be manufactured with reduced cost. The invention also relates to a method of manufacturing such a probe card with a vertical needle. The invention also relates to a test method of a wafer using such a probe card with a vertical needle.
2. Description of the Background Art
Generally, in a process of manufacturing an IC (Integrated Circuit), an LSI (Large Scale Integration) or the like, after a number of wafer chips are manufactured on a single substrate, wafer testing is performed to determine if an individual chip is good or defective before the wafer chips are cut into separate chips. Such wafer testing is generally performed with a probe card connected to an apparatus which is so-called a prober, and with a probe needle of the probe card kept in contact with a prescribed electrode (a pad) of a semiconductor chip. After the probe needle has been brought into contact with the semiconductor chip, a prescribed pressure (hereinafter referred to as a needle pressure) is applied between the probe needle and the pad (the operation is called overdriving). The overdriving allows the probe needle to slide over a pad surface, removing aluminum oxide thereon. Thus, aluminum under the aluminum oxide and the probe needle are electrically connected.
FIG. 20 is a cross section showing a probe card using a conventional cantilever type probe needle, which is disclosed in Japanese Utility Model Laying-Open No. 57-146340. The probe card includes a single printed board (hereinafter referred to as a substrate) 1. An opening 2 is formed in a middle portion of substrate 1. In a prescribed position in the opening, a plurality of probe needles 3 are radially provided on a lower surface of substrate 1, so that tips thereof are mutually aligned. Roots of probe needles 3 and a contact portion for connecting a connector (not shown), provided at an end of printed board 1 are connected through printed interconnection or wiring.
FIG. 21 shows a relation between displacement of the cantilever type probe needle and force (F). In the description, the displacement of the probe needle corresponds to a height between the tip of probe needle 3 and a surface of substrate 1, with reference to FIG. 22. On the other hand, force (F) corresponds to needle pressure (F) applied to probe needle 3 in a height direction during overdriving.
Referring to FIG. 21, there is a linear relation between displacement of probe needle and force. Generally, overdriving of about 100 .mu.m applies needle pressure of several grams (for example seven grams) to probe needle 3. Thus, the pad and probe needle 3 are electrically connected for wafer testing.
The relation in position of probe needle 3 and the pad must be carefully considered in directions of length, width and height, each requiring accuracy of about .+-.10 .mu.m. Still higher accuracy will be strictly required for a high density IC, which will be developed in the future. Presently, the relation in position of the probe needle and the pad is manually adjusted. However, the adjustment of the height of the probe needle (a distance between the tip of the probe needle and the lower surface of the substrate) is difficult.
Further, in testing a memory IC, a testing method called a simultaneous measurement test is generally employed for simultaneously testing a plurality of memory IC chips on a wafer. In most cases, the number of pads to be in contact with the probe needles is 2.times.8, which equals to sixteen in total during simultaneous measurement test. More specifically, referring to FIG. 20, one column of the cantilever type probe needles makes contact with one column.times.eight ICs and the other column of another probe needles makes contact with one column.times.eight ICs, so that 2.times.8 memory IC chips are subject to simultaneous measurement test in total.
Here, assume that there is a wafer having a certain number of IC chips and an arrangement such that all of IC chips on the wafer are tested by performing 2.times.8 simultaneous measurement test twenty times. For 4.times.4 or 4.times.8 simultaneous measurement test, the number of times that simultaneous measurement test must be performed to complete testing of all IC chips on a single wafer is reduced as follows as compared with the case for 2.times.8 simultaneous measurement test.
For 2.times.8 simultaneous measurement test, twenty times per wafer
For 4.times.4 simultaneous measurement test, fifteen times per wafer (-25%)
For 4.times.8 simultaneous measurement test, ten times per wafer (-50%)
As in 4.times.8=32 simultaneous measurement test, the number for testing is reduced as the number of chips for simultaneous measurement test increases. In addition, 4.times.4 simultaneous measurement test requires the number of times for testing smaller than that for 2.times.8 simultaneous measurement test, though both of them have the same number of IC chips for simultaneous measurement test. This is explained by an arrangement of the plurality of memory IC chips on a single wafer.
Smaller number of times for testing means that the time required for testing per wafer is shorter. The above mentioned data shows that the time required for testing can be reduced by 25% or 50% simply by changing the arrangement of IC chips on a probe card.
Reduction in the time required for testing means that the time for performing a testing step per se is reduced, resulting in reduction in a delivery time. In addition, production can be increased by 25% or 50% with the same number of testers. Therefore, increase in the number of chips for simultaneous measurement test in the probe card is a significant matter for those concerned with the manufacture of probe cards in a wafer testing section.
The above mentioned 2.times.8 and 4.times.4 arrangements, allowing simultaneous measurement test of sixteen chips, do not require any modification to testers. Thus, 4x4 arrangement, which requires smaller amount of time for testing, should have been put into practice by now. However, such three dimensional 4.times.4 arrangement, where cantilever type probe needles as shown in FIG. 23 are provided in two stages on either side, has not been actually put into practice. The reason is as follows. While the manufacture of such 4.times.4 arrangement is possible, there is a problem associated with complicated adjustment in position of probe needles and pads in directions of length, width and height, which must be performed every time after testing is completed, as well as troublesome maintenance such as repairing. As a result, cost per needle is increased several times.
The troublesome operation of the adjustment can well be understood, for example, by referring to numerical values showing precision of a probe needle. The structure of the probe needle is as follows.
Diameter of a tip of the probe needle: approximately 30 .mu.m.phi.
Pitch of the probe needle: approximately 100 .mu.m PA1 The number of probe needles: approximately 300 per column PA1 Positioning accuracy for the probe needle: approximately .+-.10 .mu.m
For 4.times.4 simultaneous measurement test, one column includes 300 probe needles. Referring to FIG. 23, take the inner two columns with longer probe needles, for example. In this case, it is considerably difficult to adjust the position of the probe needle in directions of length, width and height such that the positioning accuracy for the tip of the probe needle is always kept at approximately .+-.10 .mu.m. Thus, actually, a method of performing 2.times.8 simultaneous measurement test with a probe card having only the outer two columns has been put into practice.
Recently, especially for a DRAM (Dynamic Random Access Memory) ICs, degree of integration is dramatically increasing from 16M to 64M, then to 256M, requiring larger amount of time for testing. This is a bottleneck in the manufacturing line of ICs. Therefore, reduction in time for testing is a significant matter to be achieved.
Practical application of the arrangement of the probe card with 4.times.4, 4.times.8 or n (not less than four).times.m, which is effective for reducing the amount of time required for testing, is considered in the form of a probe card which employs a probe needle called a vertical needle (hereinafter referred to as a probe card with a vertical needle).
FIG. 24 is a cross section of the conventional probe card with a vertical needle shown in NIKKEI MICRODEVICES, September 1996, p. 104. Referring to FIG. 24, a pin 4 is vertically provided through a hole formed in a guide plate 6. The tips of the pins are freely positioned. A wafer is vertically upwardly moved from below to contact with pin 4. When a load is applied to the tip of the pin, pin 4 contracts as it has a function of spring. Further description of the conventional probe card with a vertical needle is not available, so that there still remains a number of unclear points as to its structure and the method of manufacturing the same.